Pedestal AI Accelerator IP

Embedded FPGA-Based AI Accelerator IP

An embedded FPGA IP that replaces generic DSP cells with Pedestal AI DSP cells for hardware acceleration targeting CNN, LLM, and VLM.

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Architecture differentiation

Generic FPGA DSP blocks replaced with Pedestal AI DSP blocks

The FPGA fabric retains standard programmable logic, memory, routing, and I/O resources, while conventional DSP blocks are replaced with Pedestal AI DSP blocks optimized for AI acceleration.

Traditional Embedded FPGA

Generic DSP Blocks

Traditional embedded FPGA architecture combines programmable logic, memory, routing, I/O, and conventional DSP resources.

FPGA Fabric

Programmable LogicLUT + FF Embedded MemoryBRAM Programmable LogicLUT + FF Programmable LogicLUT + FF Generic DSP Programmable LogicLUT + FF

Programmable Interconnect

I/O & Clocking

Replaced by

Pedestal Embedded FPGA AI Accelerator

Pedestal AI DSP Blocks

Pedestal retains the standard FPGA fabric while replacing conventional DSP resources with AI-optimized Pedestal AI DSP blocks.

FPGA Fabric

Programmable LogicLUT + FF Embedded MemoryBRAM Programmable LogicLUT + FF Programmable LogicLUT + FF Pedestal AI DSP Programmable LogicLUT + FF

Programmable Interconnect

I/O & Clocking

The diagram is a simplified architectural comparison. Resource placement, quantities, and implementation configuration are illustrative and do not represent a specific FPGA floorplan.

Performance points

10 TOPS, 50 TOPS, and 100 TOPS

The Embedded FPGA-Based AI Accelerator IP is associated with three currently provided performance points.

10 TOPS

50 TOPS

100 TOPS

Contact Pedestal for implementation-specific product information.

AI workload targets

Designed for CNN, LLM, and VLM hardware acceleration

Pedestal AI DSP cells target three confirmed AI workload categories within the embedded FPGA architecture.

CNN

Hardware acceleration target for convolutional neural network workloads.

LLM

Hardware acceleration target for large language model workloads.

VLM

Hardware acceleration target for vision-language model workloads.

Pedestal product context

An additional capability in Pedestal's AI portfolio

Pedestal's established NPU IP positioning remains central. The Embedded FPGA-Based AI Accelerator IP adds an embedded FPGA capability alongside Pedestal's existing AI acceleration, DSP, and ASIC/SoC-related capabilities.

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Contact Pedestal for product and implementation-specific information.

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